A magnetic random access memory (MRAM) chip is generally comprised of an array of parallel first conductive lines on a horizontal plane, an array of parallel second conductive lines on a second horizontal plane spaced above and formed in a direction perpendicular to the first conductive lines, and a magnetic tunnel junction (MTJ) formed at each location where a second conductive line crosses over a first conductive line. A first conductive line may be a word line while a second conductive line is a bit line or vice versa. Alternatively, a first conductive line may be a bottom electrode line while a second conductive line is a bit line (or word line). There may be an array of third conductive lines which is comprised of word lines (or bit lines) formed above the array of second conductive lines. Optionally, there may be an additional conductive layer that has an array of conductive lines below the array of first conductive lines. Furthermore, other devices including transistors and diodes may be formed below the array of first conductive lines.
The MTJ consists of a magnetoresistive stack of layers with a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric layer. One of the ferromagnetic layers is a pinned layer in which the magnetization (magnetic moment) direction is fixed by exchange coupling with an adjacent anti-ferromagnetic (AFM) pinning layer. The second ferromagnetic layer is a free layer in which the magnetic moment direction can be changed by external magnetic fields. The magnetic moment of the free layer may change in response to external magnetic fields which can be generated by passing currents through conductive lines. When the magnetic moment of the free layer is parallel to that of the pinned layer, there is a lower resistance for tunneling current across the dielectric layer than when the magnetic moments of the free and pinned layers are anti-parallel. The MTJ stores information as a result of having one of two different magnetic states.
In a read operation, the information is read by sensing the magnetic state (resistance level) of the MTJ through a sensing current flowing through the MTJ. During a write operation, the information is written to the MTJ by changing the magnetic state to an appropriate one by generating external magnetic fields as a result of applying bit line and word line currents.
Referring to FIG. 1, a portion of a conventional MRAM chip 1 comprised of two adjacent MRAM cells with two MTJs 7 is depicted. There is a substrate 2 upon which a first insulation layer 3a is formed. Two studs 4 are formed on the substrate 2 and in insulation layer 3a in which each stud has an overlying first conductive line 5 that is coplanar with the second insulation layer 3b. A third insulation layer 6 is formed on the first conductive lines 5 and on the second insulation layer 3b. A MTJ 7 is located above each first conductive line 5 and is connected to an overlying second conductive line 8. Typically, an MRAM chip has a plurality of first conductive lines that may be sectioned and a plurality of second conductive lines and an MTJ is formed at each location where a second conductive line crosses over a first conductive line. Typically, a fourth insulation layer 9 is deposited on the second conductive lines 8. A fifth insulation layer 10 is shown on the third insulation layer and a third conductive layer comprised of an array of third conductive lines 11 is formed within the fifth insulation layer. When the second conductive lines 8 are bit lines, the third conductive lines 11 are word lines, or vice versa. For simplicity, second conductive lines 8 are referred to as bit lines with the understanding that they can be word lines. Second conductive lines 8 and third conductive lines 11 are formed in orthogonal directions. Additionally, there are devices such as transistors and diodes in the substrate 2 which are not shown in this drawing.
Referring to FIG. 2, a typical MTJ 7 is shown which consists of a stack of layers including one or more bottom seed layers 20 such as NiFeCr formed on a conductive line 5. Next, an anti-ferromagnetic (AFM) pinning layer 21 that may be MnPt, for example, is deposited on the seed layer 20. There is a ferromagnetic “pinned” layer 22 on the AFM layer 21 that may be a composite of multiple layers including CoFe layers. The tunnel barrier layer 23 above the pinned layer 22 is generally comprised of a dielectric material such as Al2O3. Above the tunnel barrier layer 23 is a ferromagnetic “free” layer 24 which may be another composite layer that includes NiFe, for example. At the top of the MTJ stack is one or more cap layers 25. In configurations where only one cap layer is employed, the cap layer 25 is comprised of conductive material such as Ta for making an electrical contact to the subsequently formed bit line 8. This MTJ stack has a so-called bottom spin valve configuration. Alternatively, an MTJ stack may have a top spin valve configuration in which a free layer is formed on a seed layer followed by sequentially forming a tunnel barrier layer, a pinned layer, an AFM layer, and a cap layer.
The density or number of MRAM cells in an MRAM chip is determined by various factors. One factor is the lithography or patterning process that has limitations on how close two elements such as two MTJs may be fabricated. Another factor which is the primary focus of the present invention is how many MRAM cells each bit line can connect. A lower bit line resistance allows more MRAM cells to be connected by the bit line and thereby increases the chip packing density. In the MRAM chip shown in FIG. 1, the bit line resistance has a lower limit which is determined by the maximum bit line width and thickness. Both of these dimensions are set by other considerations in the MRAM chip design and fabrication. Moreover, the trend in the industry is to shrink the width of a bit line to increase packing density but unfortunately the new chip designs often lead to an increase in bit line resistance. In order to reduce bit line resistance beyond what is achieved in state of the art MRAM chips, it is desirable to modify the bit line structure to increase its cross-sectional area without compromising other aspects of device performance. Furthermore, the method for fabricating an improved bit line structure should be accomplished with existing tools and materials so as not to incur additional process cost.
A method for forming minimally spaced MRAM structures is disclosed in U.S. Pat. No. 6,682,943. The width of an opening in a lithographic pattern is reduced by inserting sidewall spacers in the opening and then filling the space with a plug that later becomes an etch mask for forming a smaller critical dimension in an insulation layer between adjacent MRAM cells.
In U.S. Pat. No. 6,365,419, a high density MRAM cell array is described in which interconnect stacks are terminated with a via. This method eliminates the need for a line termination or metallization connection that would require a minimum critical dimension below about 0.1 microns which is less than current lithographic processes can accurately reproduce in a manufacturing line.
In U.S. Pat. No. 6,545,900, memory cell zones comprised of MRAM cells and peripheral circuits are nested in one another to conserve space and increase packing density. Peripheral circuits of one row of memory cell zones project into free corners of memory cell zones in adjacent rows.
A three dimensional MRAM array is disclosed in U.S. Pat. No. 6,473,328 in which multiple layers of MRAM cells are fabricated between conductive layers comprised of lines that may be oriented in a direction that is parallel or perpendicular to lines in overlying or underlying layers. A top conductive line on one MRAM cell serves as the bottom conductive line for an overlying MRAM cell. A higher chip density is achieved since only “n+1” conductive layers are required for “n” layers of MRAM cells.